(1) Field of the Invention
The present invention relates to a boundary-free semiconductor memory device suitable for use in a multi-dimensional data processing such as video data processing.
(2) Description of the Related Art
In video data processing or the like, a video memory device is used for storing video data. Such a device often stores video data in correspondence with pictures displayed in a graphic display or the like. For video data between adjacent addresses stored in such a device, data processings or dust removing processing such as compression processing, difference processing, smoothing processing, and the like are often carried out. For such processings, in addition to the access to a desired memory cell, it is necessary to access data of memory cells in the periphery of the desired memory cell. Therefore, in a video memory or the like, a prompt access to memory cells in the periphery of a desired memory cell, as well as the memory cell per se, is required.
Also, the above-mentioned requirement is applied to a processing for accessing every word unit such as a matrix calculation, a three-dimensional data processing, as well as a processing for accessing every memory cell unit. If a function for promptly reading stored data of adjacent addresses is provided, the efficiency of these processings is improved.
There is known a semiconductor memory device in which it is possible to access memory cells in the periphery of a desired memory cell as well as the memory cell per se (see: Japanese Unexamined Patent Publication (Kokai) No. 59-180324). In this device, however, address boundaries exist, which will be later explained in detail.
There is also known an address boundary-free semiconductor memory device in which there are no address boundaries (see: Japanese Unexamined Patent Publication (Kokai) No. 59-180324). In this device, however, only the columns adjacent to the same word line can be read. In a video processing, data of a two-dimensional spread is often required. In this case, a complex operation is required, which will be also explained in detail.
There is further known an address boundary-free semiconductor memory device, in which memory cells connected to word lines adjacent to an accessed memory cell are also simultaneously and parallelly accessed (see: Japanese Unexamined Patent Publication (Kokai) No. 61-58058). In this device, however, it is extremely difficult to enlarge an accessed group of bits. Also, this device is disadvantageous from the aspects of capacity and integration, which will be later explained in detail.